Top-down fabrication optimisation of ZnO nanowire-FET by sidewall smoothing

N. A.B. Ghazali, M. Ebert, N. M.J. Ditshego, M. R.R. De Planque, H. M.H. Chong

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Abstract

This paper describes the optimisation of top-down fabrication process of the ZnO-based dual nanowire field effect transistors (NWFETs) based on the spacer method. The approach uses the top-down nanowire process with reduced sidewall roughness during pattern transfer to improve the electrical characteristics. The main feature of the process involves a reflow of the photoresist performed at a temperature of 130 °C and dry oxidation of the etched silicon sidewalls. The process optimisation leads to a significant reduction of the root-mean-square (rms) roughness of the photoresist from 23.2 nm to 3.6 nm and the ZnO nanowire rms surface roughness from 11.2 nm to 5.5 nm. The ZnO-based NWFET fabricated with the resist reflow process operates in depletion mode with a threshold voltage of - 6 V, a subthreshold slope of 0.80 V/decade, an on-off current ratio of 106, a transconductance of 5.9 nS and field effect mobility of 7.7 cm2/Vs.

Original languageEnglish
Pages (from-to)121-126
Number of pages6
JournalMicroelectronic Engineering
Volume159
DOIs
Publication statusPublished - Jun 15 2016

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All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

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