Top-down fabrication optimisation of ZnO nanowire-FET by sidewall smoothing

N. A.B. Ghazali, M. Ebert, N. M.J. Ditshego, M. R.R. De Planque, H. M.H. Chong

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

This paper describes the optimisation of top-down fabrication process of the ZnO-based dual nanowire field effect transistors (NWFETs) based on the spacer method. The approach uses the top-down nanowire process with reduced sidewall roughness during pattern transfer to improve the electrical characteristics. The main feature of the process involves a reflow of the photoresist performed at a temperature of 130 °C and dry oxidation of the etched silicon sidewalls. The process optimisation leads to a significant reduction of the root-mean-square (rms) roughness of the photoresist from 23.2 nm to 3.6 nm and the ZnO nanowire rms surface roughness from 11.2 nm to 5.5 nm. The ZnO-based NWFET fabricated with the resist reflow process operates in depletion mode with a threshold voltage of - 6 V, a subthreshold slope of 0.80 V/decade, an on-off current ratio of 106, a transconductance of 5.9 nS and field effect mobility of 7.7 cm2/Vs.

Original languageEnglish
Pages (from-to)121-126
Number of pages6
JournalMicroelectronic Engineering
Volume159
DOIs
Publication statusPublished - Jun 15 2016

Fingerprint

Field effect transistors
smoothing
Nanowires
nanowires
field effect transistors
Fabrication
fabrication
optimization
Surface roughness
Photoresists
photoresists
roughness
Transconductance
Silicon
transconductance
Threshold voltage
threshold voltage
spacers
surface roughness
depletion

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

Cite this

Ghazali, N. A.B. ; Ebert, M. ; Ditshego, N. M.J. ; De Planque, M. R.R. ; Chong, H. M.H. / Top-down fabrication optimisation of ZnO nanowire-FET by sidewall smoothing. In: Microelectronic Engineering. 2016 ; Vol. 159. pp. 121-126.
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Top-down fabrication optimisation of ZnO nanowire-FET by sidewall smoothing. / Ghazali, N. A.B.; Ebert, M.; Ditshego, N. M.J.; De Planque, M. R.R.; Chong, H. M.H.

In: Microelectronic Engineering, Vol. 159, 15.06.2016, p. 121-126.

Research output: Contribution to journalArticle

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