New QC-LDPC codes implementation on FPGA platform in Rayleigh fading environment

Farid Ghani, Abid Yahya, Abdul Kader

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    This paper presents performance of Quasi-Cyclic low-density parity-check (QC-LDPC) codes on a flat Rayleigh fading channels by employing DPSK modulation scheme. The BER curves show that large girth and diversity level robust the system performance. Moreover, Prototype architecture of the LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip. Simulation results show that the proposed QC-LDPC codes achieve a 0.1dB coding gain over randomly constructed codes and perform 1.3 dB from the Shannon-limit at a BER of 10-6 with a code rate of 0.89 for block length of 1332.

    Original languageEnglish
    Title of host publicationISCI 2011 - 2011 IEEE Symposium on Computers and Informatics
    Pages206-210
    Number of pages5
    DOIs
    Publication statusPublished - 2011
    Event2011 IEEE Symposium on Computers and Informatics, ISCI 2011 - Kuala Lumpur, Malaysia
    Duration: Mar 20 2011Mar 22 2011

    Other

    Other2011 IEEE Symposium on Computers and Informatics, ISCI 2011
    CountryMalaysia
    CityKuala Lumpur
    Period3/20/113/22/11

    Fingerprint

    Computer hardware description languages
    Rayleigh fading
    Field programmable gate arrays (FPGA)
    Fading channels
    Modulation

    All Science Journal Classification (ASJC) codes

    • Computer Networks and Communications
    • Information Systems

    Cite this

    Ghani, F., Yahya, A., & Kader, A. (2011). New QC-LDPC codes implementation on FPGA platform in Rayleigh fading environment. In ISCI 2011 - 2011 IEEE Symposium on Computers and Informatics (pp. 206-210). [5958912] https://doi.org/10.1109/ISCI.2011.5958912
    Ghani, Farid ; Yahya, Abid ; Kader, Abdul. / New QC-LDPC codes implementation on FPGA platform in Rayleigh fading environment. ISCI 2011 - 2011 IEEE Symposium on Computers and Informatics. 2011. pp. 206-210
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    title = "New QC-LDPC codes implementation on FPGA platform in Rayleigh fading environment",
    abstract = "This paper presents performance of Quasi-Cyclic low-density parity-check (QC-LDPC) codes on a flat Rayleigh fading channels by employing DPSK modulation scheme. The BER curves show that large girth and diversity level robust the system performance. Moreover, Prototype architecture of the LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip. Simulation results show that the proposed QC-LDPC codes achieve a 0.1dB coding gain over randomly constructed codes and perform 1.3 dB from the Shannon-limit at a BER of 10-6 with a code rate of 0.89 for block length of 1332.",
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    Ghani, F, Yahya, A & Kader, A 2011, New QC-LDPC codes implementation on FPGA platform in Rayleigh fading environment. in ISCI 2011 - 2011 IEEE Symposium on Computers and Informatics., 5958912, pp. 206-210, 2011 IEEE Symposium on Computers and Informatics, ISCI 2011, Kuala Lumpur, Malaysia, 3/20/11. https://doi.org/10.1109/ISCI.2011.5958912

    New QC-LDPC codes implementation on FPGA platform in Rayleigh fading environment. / Ghani, Farid; Yahya, Abid; Kader, Abdul.

    ISCI 2011 - 2011 IEEE Symposium on Computers and Informatics. 2011. p. 206-210 5958912.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

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    AU - Kader, Abdul

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    N2 - This paper presents performance of Quasi-Cyclic low-density parity-check (QC-LDPC) codes on a flat Rayleigh fading channels by employing DPSK modulation scheme. The BER curves show that large girth and diversity level robust the system performance. Moreover, Prototype architecture of the LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip. Simulation results show that the proposed QC-LDPC codes achieve a 0.1dB coding gain over randomly constructed codes and perform 1.3 dB from the Shannon-limit at a BER of 10-6 with a code rate of 0.89 for block length of 1332.

    AB - This paper presents performance of Quasi-Cyclic low-density parity-check (QC-LDPC) codes on a flat Rayleigh fading channels by employing DPSK modulation scheme. The BER curves show that large girth and diversity level robust the system performance. Moreover, Prototype architecture of the LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip. Simulation results show that the proposed QC-LDPC codes achieve a 0.1dB coding gain over randomly constructed codes and perform 1.3 dB from the Shannon-limit at a BER of 10-6 with a code rate of 0.89 for block length of 1332.

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    Ghani F, Yahya A, Kader A. New QC-LDPC codes implementation on FPGA platform in Rayleigh fading environment. In ISCI 2011 - 2011 IEEE Symposium on Computers and Informatics. 2011. p. 206-210. 5958912 https://doi.org/10.1109/ISCI.2011.5958912